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ds07-12602-2e fujitsu semiconductor data sheet copyright?2005-2006 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95110a series mb95116a/f118as/f118aw/fv100b-101 description the mb95110a series is general-purpose, single-chip microc ontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? f 2 mc-8fx cpu core instruction set that is optimum to the controllers multiplication and division instructions 16-bit arithmetic operation bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock subclock (for dual clock product) sub pll clock (for dual clock product) (continued)
mb95110a series 2 (continued) ? timer 8/16-bit compound timer 2 channels 8/16-bit ppg 2 channels 16-bit ppg timebase timer watch prescaler (for dual clock product) ? lin-uart full duplex double buffer clock asynchronous or clock synchronous serial data transfer capable ? uart/sio full duplex double buffer clock asynchronous or clock synchronous serial data transfer capable ? i 2 c* built-in wake-up function ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected ? low-power consumption (standby) mode stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o port: the number of maximum ports ? single clock product : 39 ports ? dual clock product : 37 ports port configuration ? general-purpose i/o ports (n-ch open drain) : 2 ports ? general-purpose i/o ports (cmos) : single clock product : 37 ports dual clock product : 35 ports * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specificat ion as defined by philips.
mb95110a series 3 product lineup (continued) part number parameter mb95116a mb95f118as mb95f118aw type mask rom product flash memory product rom capacity 32 kbytes 60 kbytes ram capacity 1 kbyte 2 kbytes reset output no option* 1 clock system selectable single/dual clock* 2 single clock dual clock low voltage detection reset no cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 0.1 s (at machine clock frequency 10 mhz) interrupt processing time : 0.9 s (at machine clock frequency 10 mhz) general-purpose i/o port ? single clock product : 39 ports (n-ch open drain : 2 ports, cmos : 37 ports) ? dual clock product : 37 ports (n-ch op en drain : 2 ports, cmos : 35 ports) timebase timer interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : minimum 105 ms at sub oscillation clock 32.768 khz (f or dual clock product) : minimum 250 ms wild register capable of replacing 3 bytes of rom data i 2 c master/slave sending and receiving bus error function an d arbitration function detecting transmitting direction function start condition repeated generat ion and detection functions built-in wake-up function uart/sio data transfer capable in uart/sio full duplex double buffer, variable data lengt h (5/6/7/8-bit), built-in baud rate genera- tor transfer rate : 2400 bps to 1250000 bps (at machine clock 10 mhz) nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock synchronous (sio) or clock asynchro nous (uart) serial data transfer capable lin-uart dedicated reload timer allowing a wide r ange of communication speeds to be set. full duplex double buffer. capable of serial data transfer synchr onous or asynchronous to clock signal. lin functions available as the lin master or lin slave. 8/10-bit a/d convert- er(8 channels) 8-bit or 10-bit resolution can be selected. peripheral functions
mb95110a series 4 (continued) *1 : for details of option, refer to ? mask options?. *2 : specify clock mode when ordering mask rom. note : part number of the evaluation device in mb95 110a series is mb95fv100b-101. when using it, the mcu board (mb2146-301) is required. part number parameter mb95116a mb95f118as mb95f118aw 8/16-bit compound timer (2 channels) each channel of the timer c an be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pwm function, capture function and square waveform output count clock : 7 internal clocks and external clock can be selected. 16-bit ppg pwm mode or one-shot mode can be selected. counter operating clock : 8 selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ?8-bit ppg 2 channels? or ?16-bit ppg 1 channel?. counter operating clock : eight selectable clock sources watch counter (for dual clock product) count clock : four selectable clock s ources (125ms, 250ms, 500ms, or 1s) counter value can be set from 0 to 63. (capable of counting for 1 minute when se- lecting clock source 1 second and setting counter value to 60) watch prescaler (for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (8 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected) can be used to recover from standby modes. standby mode sleep, stop, watch (for dual clock product) , and timebase timer peripheral functions
mb95110a series 5 select of oscillation stabilization wait time (mask rom product only) for the mask rom product, you can set the mask option when ordering mask rom to select the initial value of main clock oscillation stabilization wait time from among the following four values. note that the evaluation and flash memory products are fixed their initial value of main clock oscillation stabi- lization wait time at the maximum value. packages and corresponding products : available : unavailable * : under development selection of oscillation stabilization wait time remarks (2 2 ? 2) /f ch 0.5 s (at main oscillation clock 4 mhz) (2 12 ? 2) /f ch approx. 1.02 ms (at main oscillation clock 4 mhz) (2 13 ? 2) /f ch approx. 2.05 ms (at main oscillation clock 4 mhz) (2 14 ? 2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) part number package mb95116a mb95f118as mb95f118aw mb95fv100b-101 lcc-48p-m09 fpt-48p-m26 fpt-52p-m01 * bga-224p-m08
mb95110a series 6 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only the functions of the mb95110a corresponding products series but also those of other products to support software developm ent for multiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by the mb95110a series are therefore access-barred. read/write access to these access-barred addresses ma y cause peripheral resources supposed to be unused to operate, resulting in unexpected ma lfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or written unexpectedly). note that the values read from barred addresses are different between the evaluation product and the flash memory or mask rom product. therefore, the data must not be used for software processing. the evaluation product do not support the functions of some bits in single-byte registers. read/write access to these bits does not cause hardware malfunctions. the evaluation, flash memory, and mask rom products are designed to behave completely the same way in terms of hardware and software. ? difference of memory spaces if the amount of memory on the evaluation product is di fferent from that of the flash memory or mask rom product, carefully check the differ ence in the amount of memory from the model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption the current consumption of flash memory pr oduct is greater than for mask rom product. for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? package dimensions?. ? operating voltage the operating voltage are different among the ev aluation, flash memory, and mask rom products. for details of operating voltage, refer to ? electrical characteristics? ? difference between rst and mod pins the input type of rst and mod pins is cmos input on the flash memory product. the rst and mod pins are hysteresis inputs on the mask ro m product. a pull - down resistor is provided for the mod pin of the mask rom product.
mb95110a series 7 pin assignments (continued) (top view) (lcc-48p-m09) * : single clock product is general-purpose port, and dual clock product is subclock oscillation pin. 1 2 3 4 5 6 7 8 9 10 11 12 p65/sck p66/sot p67/sin p 37/an07 p 36/an06 p 35/an05 p 34/an04 p 33/an03 p 32/an02 p 31/an01 p 30/an00 avss 37 36 35 34 33 32 31 30 29 28 27 26 p06/int0 6 p05/int0 5 p04/int0 4 p03/int0 3 p02/int0 2 p01/int0 1 p00/int0 0 rst pg1/x0a * pg2/x1a * pg0 vcc 14 13 15 16 17 18 19 20 21 22 23 24 25 48 47 46 45 44 43 42 41 40 39 38 avcc p24/ec0 p23/to01 p22/to00 p 21/ppg01 p 20/ppg00 p51/sda0 p50/scl0 mod x0 x1 vss p64/ec1 p63/to11 p62/to10 p61/ppg11 p60/ppg10 p15 p14/ppg0 p13/trg0/adt g p12/uck0 p11/uo0 p10/ui0 p07/int07
mb95110a series 8 (continued) (top view) (fpt-48p-m26) * : single clock product is general-purpose port, and dual clock product is subclock oscillation pin. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p65/sck p66/sot p67/sin p 37/an07 p 36/an06 p 35/an05 p 34/an04 p 33/an03 p 32/an02 p 31/an01 p 30/an00 avss avcc p24/ec0 p23/to01 p22/to00 p 21/ppg01 p 20/ppg00 p51/sda0 p50/scl0 mod x0 x1 vss p06/int0 6 p05/int0 5 p04/int0 4 p03/int0 3 p02/int0 2 p01/int0 1 p00/int0 0 rst pg1/x0a * pg2/x1a * pg0 vcc p64/ec1 p63/to11 p62/to10 p61/ppg11 p60/ppg10 p15 p14/ppg0 p13/trg0/adt g p12/uck0 p11/uo0 p10/ui0 p07/int07
mb95110a series 9 (continued) (top view) (fpt-52p-m01) * : single clock product is general-purpose port, and dual clock product is subclock oscillation pin. 52 51 50 49 48 47 46 45 44 43 42 41 14 15 16 17 18 19 20 21 22 23 24 25 40 26 p65/sck p66/sot p67/sin p 37/an07 p 36/an06 p 35/an05 nc p 34/an04 p 33/an03 p 32/an02 p 31/an01 p 30/an00 avss 1 2 3 4 5 6 7 8 9 10 11 12 13 avcc p24/ec0 p23/to01 p22/to00 p 21/ppg01 p 20/ppg00 nc p51/sda0 p50/scl0 mod x0 x1 vss p06/int0 6 p05/int0 5 p04/int0 4 p03/int0 3 p02/int0 2 p01/int0 1 nc p00/int0 0 rst pg1/x0a * pg2/x1a * pg0 vcc 39 38 37 36 35 34 33 32 31 30 29 28 27 p64/ec1 p63/to11 p62/to10 p61/ppg11 p60/ppg10 p15 nc p14/ppg0 p13/trg0/adt g p12/uck0 p11/uo0 p10/ui0 p07/int07
mb95110a series 10 pin description (continued) pin no. pin name i/o circuit type* 3 function lqfp *1 lqfp *2 1 1 p65/sck k general-purpose i/o port. the pin is shared with lin-uart clock i/o. 2 2 p66/sot general-purpose i/o port. the pin is shared with lin-uart data output. 33p67/sinl general-purpose i/o port. the pin is shared with lin-uart data input. 4 4 p37/an07 j general-purpose i/o port. the pins are shared with a/d converter analog input. 5 5 p36/an06 6 6 p35/an05 7 8 p34/an04 8 9 p33/an03 910p32/an02 10 11 p31/an01 11 12 p30/an00 12 13 avss ? a/d converter power supply pin (gnd) 13 14 avcc ? a/d converter power supply pin 14 15 p24/ec0 h general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.0 clock input. 15 16 p23/to01 general-purpose i/o port. the pins are shared with 8/16-bit compound timer ch.0 output. 16 17 p22/to00 17 18 p21/ppg01 general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.0 output. 18 19 p20/ppg00 19 21 p51/sda0 i general-purpose i/o port. the pin is shared with i 2 c ch.0 data i/o. 20 22 p50/scl0 general-purpose i/o port. the pin is shared with i 2 c ch.0 clock i/o. 21 23 mod b operating mode designation pin 22 24 x0 a main clock input oscillation pin 23 25 x1 main clock input/output oscillation pin 24 26 vss ? power supply pin (gnd) 25 27 vcc ? power supply pin 26 28 pg0 h general-purpose i/o port.
mb95110a series 11 (continued) *1 : fpt-48p-m26 *2 : fpt-52p-m01 *3: for the i/o circuit type, refer to ? i/o circuit type? pin no. pin name i/o circuit type* 3 function lqfp *1 lqfp *2 27 29 pg2/x1a h/a single clock product is general-purpose port (pg2) . dual clock product is sub clock inpu t/output oscillation pin (32 khz). 28 30 pg1/x0a single clock product is general-purpose port (pg1) . dual clock product is sub clock input oscillation pin (32 khz). 29 31 rst b? reset pin 30 32 p00/int00 c general-purpose i/o port. the pins are shared with external interrupt input. large current port. 31 34 p01/int01 32 35 p02/int02 33 36 p03/int03 34 37 p04/int04 35 38 p05/int05 36 39 p06/int06 37 40 p07/int07 38 41 p10/ui0 g general-purpose i/o port. the pin is shared with uart/sio ch.0 data input. 39 42 p11/uo0 h general-purpose i/o port. the pin is shared with uart/sio ch.0 data output. 40 43 p12/uck0 general-purpose i/o port. the pin is shared with uart/sio ch.0 clock i/o. 41 44 p13/trg0/ adtg general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 trigger input (trg0) and a/d trigger input (adtg). 42 45 p14/ppg0 general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 output. 43 47 p15 general-purpose i / o port. 44 48 p60/ppg10 k general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.1 output. 45 49 p61/ppg11 46 50 p62/to10 general-purpose i/o port. the pins are shared with 8/16-bit compound timer ch.1 output. 47 51 p63/to11 48 52 p64/ec1 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.1 clock input. ? 7, 20, 33, 46 nc ? internal connect pin. be sure this pin is left open.
mb95110a series 12 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance value : approx. 1 m ? low-speed side feedback resistance : approx. 24 m ? (evaluation product : approx. 10 m ? ) dumping resistance : approx. 144 k ? (evaluation product : without dumping resistance) b only for input hysteresis input only for mask rom product with pull-down resistor only for mask rom product b? hysteresis input only for mask rom product c cmos output hysteresis input g cmos output cmos input hysteresis input with pull-up control x 0 (x0a) x1 (x1a) n-ch standby control clock inpu t r mode input reset input p-ch n-ch standby control external interrupt enable digital output digital output hysteresis inpu t r p-ch p-ch n-ch pull-up control standby control digital output digital output hysteresis inpu t cmos input
mb95110a series 13 (continued) type circuit remarks h cmos output hysteresis input with pull-up control i n-ch open drain output cmos input hysteresis input j cmos output hysteresis input analog input with pull-up control k cmos output hysteresis input l cmos output cmos input hysteresis input p-ch p-ch n-ch r pull-up control standby control digital output digital output hysteresis inp ut n-ch standby control digital output hysteresis inpu t cmos input r p-ch p-ch n-ch pull-up control analog input a/d control standby control digital output digital output hysteresis inpu t p-ch n-ch standby control digital output digital output hysteresis inp ut p-ch n-ch standby control digital output digital output hysteresis inp ut cmos input
mb95110a series 14 handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not ex ceeded when they are used. latch-up may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current incr eases rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc ) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system power supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the v cc power-supply voltage. for stabilization, in principle, keep the variation in v cc ripple (p-p value) in a commercial frequency range (50 hz/60 hz) not to exceed 10 % of the standard v cc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms dur ing a momentary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizat ion wait time is required for power-on reset, wake-up from subclock mode or stop mode. pin connection ? treatment of unused input pin leaving unused input pins unconnect ed can cause abnormal operation or latch-up, leaving to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potentia l are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro- magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between v cc and v ss pins near this device.
mb95110a series 15 ? mode pin (mod) connect the mode pin directly to v cc or v ss . to prevent the device unintentionally entering test mode du e to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to v cc or v ss and to provide a low-impedance connection. ? analog power supply always set the same potential to av cc and v cc . when v cc > av cc , the current may flow through the an00 to an07 pins.
mb95110a series 16 programming flash memory microcontrollers using parallel pro- grammer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note: for information on applicable adapter models and parallel programmers, contact the following: flash support group, inc. tel: +81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to add resses used for cpu access and programming by the parallel programmer as follows: package applicable adapter model parallel programmers fpt-48p-m26 tef110-118f37ap af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-52p-m01 tef110-95f118pmc lcc-48p-m09 tef100-118f41ap *: programmer addresses are equivalent to cpu addre sses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory . flash memory cpu address writer address * sa1 (4 kbytes) 1000 h 71000 h 1fff h 71fff h sa2 (4 kbytes) 2000 h 72000 h 2fff h 72fff h sa3 (4 kbytes) 3000 h 73000 h 3fff h 73fff h sa4 (16 kbytes) 4000 h 74000 h 7fff h 77fff h sa5 (16 kbytes) 8000 h 78000 h bfff h 7bfff h sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h lower bank upper bank
mb95110a series 17 ? programming method 1) set the type code of the parallel programmer to ?17226?. 2) load program data to programmer addresses 71000 h to 7ffff h . 3) programmed by parallel programmer.
mb95110a series 18 block diagram p15 p65/sck p67/sin av cc av ss p50/scl0 p51/sda0 p30/an00 to p37/an07 p12/uck0 p62/to10 p61/ppg11 p60/ppg10 p63/to11 p00/int00 to p07/int07 p10/ui0 p64/ec1 p66/sot rst x0,x1 p14/ppg0 p13/trg0/adtg p20/ppg00 p21/ppg01 p22/to00 p23/to01 p24/ec0 p11/uo0 uart/sio 16-bit ppg 8/16-bit ppg ch0 8/10-bit a/d converter i 2 c 8/16-bit ppg ch1 rom ram f 2 mc-8fx cpu port port 8/16-bit compound timer ch0 8/16-bit compound timer ch1 interrupt control wild register reset control clock control watch prescaler watch counter external interrupt internal bus pg2/x1a* pg1/x0a* pg0 lin-uart mod, v cc , v ss * : single clock product is general-purpose port, and dual clock product is subclock oscillation pin. other pins
mb95110a series 19 cpu core 1. memory space memory space of the mb95110a series is 64 kbytes and consists of i/o area, data area, and program area. the memory space includes special-purpose areas su ch as the general-purpose registers and vector table. memory map of the mb95110a series shown in below. 0000 h 0080 h 0100 h 0200 h 0880 h 0f80 h 1000 h ffff h flash 60 kbytes mb95f118as mb95f118aw i/o ram 2 kbytes extension i/o 0000 h 0080 h 0100 h 0200 h 0f80 h 1000 h ffff h extension i/o ram 3.75 kbytes mb95fv100b-101 i/o 0000 h 0080 h 0100 h 0200 h 0480 h 0f80 h 8000 h ffff h rom 32 kbytes mb95116a i/o ram 1 kbyte extension i/o 1000 h register register register access prohibited access prohibited access prohibited flash 60 kbytes memory map
mb95110a series 20 2. register the mb95110a series has two types of registers; dedica ted registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for us e as a condition code register (ccr). (refer to the diagram below.) program counter (pc) : a 16-bit register to indicate locati ons where instructions are stored. accumulator (a) : a 16-bit register for temporary storage of arithmetic operations. in the case of an 8-bit data processing instruction, the lower one byte is used. temporary accumulator (t) : a 16-bit register which performs arithm etic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower one byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit register to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc a t ix ep sp ps 16-bit : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h p s rp ccr bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 dp2 dp1 dp0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp structure of the program status
mb95110a series 21 the rp indicates the address of th e register bank currently being used . the relationship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic opera tion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is set to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by this bit. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower
mb95110a series 22 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. one bank contains eight registers. up to a total of 32 banks can be used on the mb95110a series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 t his address = 0100 h + 8 (rp) r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1f8 h 1ff h bank 31 bank 0 8-bit register bank configuration 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance.
mb95110a series 23 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler cont rol register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (disabled) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h pdr3 port 3 data register r/w 00000000 b 0011 h ddr3 port 3 direction register r/w 00000000 b 0012 h , 0013 h ? (disabled) ?? 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0029 h ? (disabled) ?? 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ?? 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h pul3 port 3 pull-up register r/w 00000000 b 0030 h to 0034 h ? (disabled) ??
mb95110a series 24 (continued) address register abbreviation register name r/w initial value 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 contro l status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 contro l status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 contro l status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 contro l status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h to 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg status control re gister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg status control re gister (lower byte) ch.0 r/w 00000000 b 0044 h to 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit c ontrol register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit c ontrol register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit c ontrol register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit c ontrol register ch.6/ch.7 r/w 00000000 b 004c h to 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h smc10 uart/sio serial mode control register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 005f h ? (disabled) ??
mb95110a series 25 (continued) address register abbreviation register name r/w initial value 0060 h ibcr00 i 2 c bus control register 0 ch.0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch.0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch.0 r 00000000 b 0063 h iddr0 i 2 c data register ch.0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch.0 r/w 00000000 b 0065 h iccr0 i 2 c clock control register ch.0 r/w 00000000 b 0066 h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? (mirror of register bank pointer (rp) and direct bank pointer (dp) ) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b
mb95110a series 26 (continued) address register abbreviation register name r/w initial value 0f86 h wrarh2 wild register address setting re gister (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting re gister (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 contro l status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 contro l status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 contro l status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 contro l status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg starting register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h to 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter re gister (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter regi ster (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer re gister (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer re gister (lower byte) ch.0 r/w 11111111 b
mb95110a series 27 (continued) r/w access symbols initial value symbols note : do not write to the ? (d isabled) ?. reading the ? (disabled ) ? returns an undefined value. address register abbreviation register name r/w initial value 0fb0 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate gene rator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate gene rator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler selection register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h to 0fc2 h ? (disabled) ?? 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b 0fc4 h to 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95110a series 28 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] (unused) irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch.0 irq16 ffda h ffdb h l16 [1 : 0] (unused) irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler/counter irq20 ffd2 h ffd3 h l20 [1 : 0] (unused) irq21 ffd0 h ffd1 h l21 [1 : 0] 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95110a series 29 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 vcc, avcc vss ? 0.3 vss + 4.0 v * 2 input voltage* 1 v i1 vss ? 0.3 vss + 4.0 v other than p50, p51* 3 v i2 vss ? 0.3 vss + 6.0 p50, p51 output voltage* 1 v o vss ? 0.3 vss + 4.0 v * 3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than p00 to p07 i ol2 15 p00 to p07 ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p00 to p07 i oh2 ? 15 p00 to p07 ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb95110a series 30 (continued) *1 : the parameter is based on av cc = v ss = 0.0 v. *2 : apply equal potential to avcc and vcc. *3 : v i1 and v o should not exceed v cc + 0.3 v. v i1 must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i1 rating. *4 : ? applicable to pins : p00 to p07, p10 to p15, p20 to p24, p30 to p37, pg0 ? use within recommended operating conditions. ? use at dc voltage (current). ?+ b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistanc e should be set so that when the + b signal is applied the input current to the microcontroller pin does not ex ceed rated values, either instant aneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and in crease the potential at the vcc pin, and this may affect other devices. ? note that if the + b signal is inputted when the microcontroller po wer supply is off (not fixed at 0 v), the power supply is provided from the pins, so th at incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits : warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch vcc r input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95110a series 31 2. recommended operating conditions (av ss = v ss = 0.0 v) (continued) parameter symbol pin name conditions value unit remarks min typ max power supply voltage v cc , av cc ?? 1.8* 1 ? 3.3 v at normal operating, flash memory product, t a = ? 10 c to + 85 c 1.8* 1 ? 3.6 at normal operating, mask rom product, t a = ? 10 c to + 85 c 2.0* 1 ? 3.3 at normal operating, flash memory product, t a = ? 40 c to + 85 c 2.0* 1 ? 3.6 at normal operating, mask rom product, t a = ? 40 c to + 85 c 2.6 ? 3.6 mb95fv100b-101, t a = + 5 c to + 35 c 1.5 ? 3.3 retain status of stop mode operation, flash memory product 1.5 ? 3.6 retain status of stop mode operation, mask rom product ?h? level input voltage v ih1 p10, p67 *2 0.7 vcc ? vcc + 0.3 v at selecting of cmos input level (hysteresis input) v ih2 p50, p51 *2 0.7 vcc ? vss + 5.5 v at selecting of cmos input level (hysteresis input) v ihs1 p00 to p07, p10 to p15, p20 to p24, p30 to p37, p60 to p67, pg0, pg1* 2 , pg2* 2 *2 0.8 vcc ? vcc + 0.3 v hysteresis input v ihs2 p50, p51 *2 0.8 vcc ? vss + 5.5 v hysteresis input v ihm rst , mod ? 0.7 vcc ? vcc + 0.3 v cmos input (flash memory product) ? 0.8 vcc ? vcc + 0.3 v hysteresis input (mask rom product)
mb95110a series 32 (continued) *1 : the values vary with the operating frequency. *2 : p10, p50, p51, and p67 can switch the input level to either the ?cmos input level? or ?hysteresis input level?. the switching of the input level can be set by the input level selection register (ilsr). warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol pin name conditions value unit remarks min typ max ?l? level input voltage v il p10, p50, p51, p67 *2 vss ? 0.3 ? 0.3 vcc v at selecting of cmos input level (hysteresis input) v ils p00 to p07, p10 to p15, p20 to p24, p30 to p37, p50, p51, p60 to p67, pg0, pg1* 2 , pg2* 2 *2 vss ? 0.3 ? 0.2 vcc v hysteresis input v ilm rst , mod ? vss ? 0.3 ? 0.3 vcc v cmos input (flash memory product) ? vss ? 0.3 ? 0.2 vcc v hysteresis input (mask rom product) operating temperature t a ?? ? 40 ? + 85 c
mb95110a series 33 3. dc characteristics (vcc = avcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name conditions value unit remarks min typ max ?h? level output voltage v oh1 output pin other than p00 to p07 i oh = ? 4.0 ma 2.4 ?? v mb95fv100b-101 a conditional : i oh = ? 2.0 ma v oh2 p00 to p07 i oh = ? 8.0 ma 2.4 ?? v mb95fv100b-101 a conditional : i oh = ? 5.0 ma ?l? level output voltage v ol1 output pin other than p00 to p07 i ol = 4.0 ma ?? 0.4 v mb95fv100b-101 a conditional : i ol = 3.0 ma v ol2 p00 to p07 i ol = 12 ma ?? 0.4 v mb95fv100b-101 a conditional : i ol = 8.0 ma open drain output applica- tion voltage v d p50, p51 ? vss ? 0.3 ? vss + 5.5 v input leakage current (hi-z output leakage current) i li port other than p50, p51 0.0 v < v i < vcc ? 5 ? + 5 a when no pull-up prohibition setting open drain output leakage current i liod p50, p51 0.0 v < v i < vss + 5.5 v ?? + 5 a pull-up resistor r pull p10 to p15, p20 to p24, p30 to p37, pg0, pg1* 1 , pg2* 1 v i = 0.0 v 25 50 100 k ? when pull-up permission setting pull-down resistor r mod mod v i = vcc 50 100 200 k ? mask rom product only power supply current* 2 i cc v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 11 14 ma flash memory product ? 7.3 10 ma mask rom product ? 30 35 ma flash memory product (at flash writing and erasing) i ccs f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 6 ma
mb95110a series 34 (continued) (vcc = avcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : single clock products only *2 : the power-supply current is de termined by the external clock. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter symbol pin name conditions value unit remarks min typ max power supply current* 2 i ccl v cc ( external clock operation ) f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) , t a = + 25 c ? 25 35 a i ccls f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 715 a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ? 210 a flash memory product ? 15 a mask rom product i ccmpll f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 10 14 ma flash memory product ? 6.7 10 ma mask rom product i ccspll f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 190 250 a i cts f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.4 0.5 ma i cch sub stop mode t a = + 25 c ? 15 a i a avcc f ch = 10 mhz at a/d converting ? 1.3 2.2 ma i ah f ch = 10 mhz at a/d converting stop t a = + 25 c ? 15 a input capacitance c in other than avcc, avss, vcc, and vss f = 1 mhz ? 515pf
mb95110a series 35 4. ac characteristics (1) clock timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 10 mhz when using main oscilla- tion circuit 1 ? 20 mhz when using external clock 3 ? 10 mhz main pll multiplied by 1 3 ? 5 mhz main pll multiplied by 2 3 ? 4 mhz main pll multiplied by 2.5 f cl x0a, x1a ? 32.768 ? khz when using sub oscilla- tion circuit ? 32.768 ? khz when using sub pll flash memory product : vcc = 2.3 v to 3.3 v mask rom product : vcc = 2.3 v to 3.6 v clock cycle time t hcyl x0, x1 100 ? 1000 ns when using main oscilla- tion circuit 50 ? 1000 ns when using sub oscilla- tion circuit t lcyl x0a, x1a ? 30.5 ? s subclock input clock pulse width t wh1 t wl1 x0 10 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95110a series 36 t hcyl t wh1 t cr 0.2 v cc x 0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 x0 x1 f ch x0 f ch x1 microcontroller microcontroller c1 c2 ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.1 v cc x 0a 0.8 v cc 0.8 v cc 0.1 v cc 0.1 v cc t cf t wl2 x0a x1a f cl x0a f cl x1a microcontroller microcontroller c1 c2 ? figure of subclock inpu t port external connection when using a crystal or ceramic oscillator when using external clock open
mb95110a series 37 (2) source clock/machine clock (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock division ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machine clock division ra tio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the source clock can be selected as follow. ? main clock divided by 2 ? pll multiplication of main clock (select from 1, 2, 2.5 multiplication) ? subclock divided by 2 ? pll multiplication of subclock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follow. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock* 1 (clock before setting division) t sclk ? 100 ? 2000 ns when using main clock min : f ch = 10 mhz, pll multiplied by 1 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using subclock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.5 ? 10.0 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using subclock machine clock* 2 (minimum instruction execution time) t mclk ? 100 ? 32000 ns when using main clock min : f sp = 10 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using subclock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 10.000 mhz when using main clock f mpl 1.024 ? 131.072 khz when using subclock
mb95110a series 38 ? outline of clock generation block f ch ( main oscillation) f cl (sub oscillation) divided by 2 main pll 1 2 2.5 divided by 2 sub pll 2 3 4 sclk ( source clock ) mclk ( machine clock ) clock mode select bit ( sycc : scs1, scs0 ) division circuit 1 1/4 1/8 1/16
mb95110a series 39 ? operating voltage - oper ating frequency (when t a = ? 10 c to + 85 c) ? mb95116a ? mb95f118as, mb95f118aw 131.072 khz 16.384 khz 1.8 3.6 2.3 32 khz 10 mhz 0.5 mhz 3.6 1.8 5 mhz 3 mhz 2.2 sub pll operation guarantee range source clock frequency (f sp ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range 131.072 khz 16.384 khz 1.8 3.3 2.3 32 khz 10 mhz 0.5 mhz 3.3 1.8 7.5 mhz 3 mhz 2.2 sub pll operation guarantee range source clock frequency (f sp ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mod e operation guarantee range
mb95110a series 40 ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) ? mb95116a ? mb95f118as, mb95f118aw 131.072 khz 16.384 khz 2.0 3.6 2.3 32 khz 10 mhz 0.5 mhz 3.6 2.0 5 mhz 3 mhz 2.2 sub pll operation guarantee range source clock frequency (f sp ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mod e operation guarantee range 131.072 khz 16.384 khz 2.0 3.3 2.3 32 khz 10 mhz 0.5 mhz 3.3 2.0 7.5 mhz 3 mhz 2.2 sub pll operation guarantee range source clock frequency (f sp ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mod e operation guarantee range
mb95110a series 41 ? operating voltage - op erating frequency (when t a = + 5 c to + 35 c) ? mb95fv100b-101 ? main pll operation frequency 10 mhz 0.5 mhz 2.6 3 mhz 3.6 7.5 mhz 131.072 khz 16.384 khz 2.6 32 khz 3.6 operating voltage (v) operating voltage (v) source clock frequency (f sp ) main clock operation guarantee range pll operation guarantee range pll operation guarantee range source clock frequency (f sp ) sub pll , sub clock mode and watch mode operation guarantee range main clock mode and main pll mode operation guarantee range 10 mh z 4 mhz 3 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 3 mhz 4 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 10 mhz 7 .5 mhz main clock frequency ( f mp ) source clock frequency (f sp ) 2.5 2 1
mb95110a series 42 (3) external reset (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation time of oscillator is the time that the amp litude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in cerami c oscillators, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 2 t mclk * 1 ? ns at stop mode, subclock mode, sub sleep mode, and watch mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 2 t mclk rst x0 oscillation stabilization wait time execute instruction oscillation time of oscillator 90% of amplitude internal operating clock i nternal reset ? at normal operating ? at stop mode, subclock mode, sub sleep mode, watch mode, and power-on
mb95110a series 43 (4) power-on reset (avss = vss = 0.0 v, t a = ? 40 c to + 85 c) note : the power supply must be turned on within the selected oscillation stabilization time. note : sudden change of power supply voltage may activate the power-on re set function. when changing power supply voltages during operation, set the slope of rising within 20 mv/ms as shown below. parameter symbol conditions value unit remarks min max power supply rising time t r ?? 36 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 1.5 v 0.2 v v cc v cc 1 .5 v v ss limiting the slope of rising within 20 mv/ms is recommended. hold condition in stop mode
mb95110a series 44 (5) peripheral input timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit remarks min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, trg0/adtg 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih i nt00 to int07, e c0, ec1, t rg0/adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95110a series 45 (6) uart/sio, serial i/o timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit remarks min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v u ck0 u o0 u i0 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v u ck0 u o0 u i0 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? internal shift clock mode ? external shift clock mode
mb95110a series 46 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95110a series 47 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v s ck s ot s in t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slove t ivshe t shixe 2.4 v 0.8 v t r t f s ck s ot s in t slsh t shsl 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95110a series 48 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95110a series 49 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v s ck s ot s in t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc t shove t ivsle t slixe 2.4 v 0.8 v t f t r s ck s ot s in t shsl t slsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc internal shift clock mode external shift clock mode
mb95110a series 50 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 0.8 v 0.8 v t shovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovli t ivsli t slixi
mb95110a series 51 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl 5 t mclk * 3 ? ns sck sot hold time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns s ck s ot s in 2.4 v 2.4 v 0.8 v t slovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovhi t ivshi t shixi
mb95110a series 52 (8) i 2 c timing (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the device dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter sym- bol pin name conditions value unit re- marks standard- mode fast-mode min max min max scl clock frequency f scl scl0 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl0 sda0 4.0 ? 0.6 ? s scl clock ?l? width t low scl0 4.7 ? 1.3 ? s scl clock ?h? width t high scl0 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl0 sda0 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl0 sda0 0 3.45* 2 00.9* 3 s data setup time sda scl t su;dat scl0 sda0 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl0 sda0 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl0 sda0 4.7 ? 1.3 ? s s da0 s cl0 t wakeup t hd;sta t hd;dat t hd;sta t su;sta t low t su;dat t high t su;sto t buf
mb95110a series 53 (vcc = 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl0 r = 1.7 k ? , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0 (nm / 2) t mclk ? 20 (nm / 2 ) t mclk + 20 ns master mode start condition hold time t hd;sta scl0 sda0 ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl0 sda0 (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl0 sda0 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl0 sda0 ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0 (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl0 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception stop condition detection t su;sto scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl0 sda0 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0 sda0 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0 sda0 t low ? 3 t mclk ? 20 ? ns at slave transmission mode
mb95110a series 54 (continued) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : ? refer to ? (2) source clock/machine clock? for t mclk . ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of clock control register (iccr) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of clock control register (iccr) . ? actual timing of i 2 c is determined by m and n valu es set by the machine clock (t mclk ) and cs4 to cs0 of iccr0 register. ? standard-mode : m and n can be set at the range : 0.9 mhz < t mclk (machine clock) < 10 mhz. setting of m and n limits the machin e clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode : m and n can be set at the range : 3.3 mhz < t mclk (machine clock) < 10 mhz. setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condition value* 2 unit remarks min max data hold time t hd;dat scl0 sda0 r = 1.7 k ? , c = 50 pf* 1 0 ? ns at reception data setup time t su;dat scl0 sda0 t mclk ? 20 ? ns at reception sda scl (at wake-up function) t wakeup scl0 sda0 oscillation stabilization wait time + 2 t mclk ? 20 ? ns
mb95110a series 55 5. a/d converter (1) a/d converter electrical characteristics (avcc = vcc = 1.8 v to 3.3 v [flash memory product], avcc = vcc = 1.8 v to 3.6 v [mask rom product], avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot avss ? 1.5 lsb avss + 0.5 lsb avss + 2.5 lsb v flash memory product : 2.7 v avcc 3.3 v mask rom product : 2.7 v avcc 3.6 v avss ? 0.5 lsb avss + 1.5 lsb avss + 3.5 lsb v 1.8 v avcc < 2.7 v full-scale transition voltage v fst avcc ? 3.5 lsb avcc ? 1.5 lsb avcc + 0.5 lsb v flash memory product : 2.7 v avcc 3.3 v mask rom product : 2.7 v avcc 3.6 v avcc ? 2.5 lsb avcc ? 0.5 lsb avcc + 1.5 lsb v 1.8 v avcc < 2.7 v compare time ? 1.3 ? 140 s flash memory product : 2.7 v avcc 3.3 v mask rom product : 2.7 v avcc 3.6 v 20 ? 140 s 1.8 v avcc < 2.7 v sampling time ? 0.4 ? s flash memory product : 2.7 v avcc 3.3 v mask rom product : 2.7 v avcc 3.6 v ex- ternal impedance < at 1.8 k ? 30 ? s 1.8 v avcc < 2.7 v external impedance < at 14.8 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain avss ? avcc v reference voltage ? avss + 1.8 ? avcc v avcc pin reference voltage supply current i r ? 400 600 a avcc pin, during a/d operation i rh ?? 5 a avcc pin, at stop mode
mb95110a series 56 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample a nd hold capacitor is insufficient, adversely affecting a/ d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |av cc ? av ss | becomes smaller, values of relative errors grow larger. r c during sampling : on analog input pin comparator note : the values are reference values. ? analog input equivalent circuit rc 2.7 v avcc 3.6 v 1.7 k ? (max) 14.5 pf (max) 1.8 v avcc < 2.7 v 84 k ? (max) 25.2 pf (max) 0 5 10 15 20 25 30 35 4 0 0 10 20 30 40 50 60 70 80 90 1 00 0123 4 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time avcc 2.7 v avcc 1.8 v avcc 2.7 v
mb95110a series 57 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, anal og voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straight line connecting the zero tran sition point (?00 0000 0000? ?00 0000 0001?) of a device and the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss av c c 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h av ss v nt av c c {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = av cc ? av ss 1024 [lsb] total error of digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output digital output analog input analog input n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. (v) actual conversion characteristic actual conversion characteristic ideal characteristics
mb95110a series 58 (continued) av ss av c c 0 01 h 0 02 h 0 03 h 0 04 h av ss av c c 3 fc h 3 fd h 3 fe h 3ff h av ss av c c 001 h 002 h 003 h 004 h 3 fd h 3 fe h 3 ff h {1 lsb n + v ot } v nt av ss av cc v nt n ? 2 n ? 1 n n + 1 v ( n + 1 ) t full-scale transition error digital output analog input zero transition error digital output analog input differential linear error linearity error digital output digital output analog input analog input linear error in digital output n = v nt ? {1 lsb n + v ot } 1 lsb n : a/d converter digital output value v nt : a voltage at which digita l output transits from (n ? 1) to n. v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = av cc ? 1.5 lsb [v] differential linear error in digital output n = v (n + 1) t ? v nt 1 lsb ? 1 actual conversion characteristic actual conversion characteristic v ot (measurement value) ideal characteristics actual conversion characteristic actual conversion characteristic ideal characteristics v fst (measurement value) actual conversion characteristic actual conversion characteristic ideal characteristics v fst (measurement value) v ot (measurement value) actual conversion characteristic actual conversion characteristic ideal characteristics
mb95110a series 59 6. flash memory program/erase characteristics *1 : t a = +25 c, vcc = 3.0 v, 10000 cycles *2 : t a = +85 c, vcc = 2.7 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max sector erase time (4 kbytes sector) ? 0.2* 1 3.0* 2 s excludes 00 h programming prior erasure sector erase time (16 kbytes sector) ? 0.5* 1 12.0* 2 s excludes 00 h programming prior erasure byte programming time ? 32 3600 s excludes system-level overhead erase/program cycle 10000 ?? cycle power supply voltage at erase/program 2.7 ? 3.3 v flash data retention time 20* 3 ?? year average t a = + 85 c
mb95110a series 60 example characteristics ? mb95116a current characteristics 12 10 8 6 4 2 0 12345 i cc 2 vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 3 2.5 2 1.5 1 0.5 0 12345 i cc 32 vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 7 6 5 4 3 2 1 0 12345 i cc 2s vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 3 2.5 2 1.5 1 0.5 0 12345 i cc 32s vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 18 16 14 12 10 8 6 4 2 0 12345 i ccl , i ccl s, i cct vs v cc (f cl = 32.768 kh z) v cc (v) l ccl i ccl s i cct 3 000 2 500 2 000 1 500 1 000 500 0 1234 5 i cch vs v cc v cc (v) i cch i cc 2 (ma) i cc 32 (ma) i cc 2s (ma) i cc 32s (ma) i ccl , i ccl s, i cct ( a) i cch ( a)
mb95110a series 61 ? mb95f118as/aw current characteristics 18 16 14 12 10 8 6 4 2 0 12345 i cc 2 vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 4 3.5 3 2.5 2 1.5 1 0.5 0 12345 i cc 32 vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 7 6 5 4 3 2 1 0 12345 i cc 2s vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 3 2.5 2 1.5 1 0.5 0 12345 i cc 32s vs v cc v cc (v) f ch = 20 mh z f ch = 16 mh z f ch = 8 mh z f ch = 4 mh z f ch = 2 mh z 4 0 3 5 3 0 2 5 2 0 1 5 1 0 5 0 12345 i ccl , i ccl s, i cct vs v cc (f cl = 32.768 kh z) v cc (v) l ccl i ccl s i cct 3 000 2 500 2 000 1 500 1 000 500 0 1234 5 i cch vs v cc v cc (v) i cch i cc 2 (ma) i cc 32 (ma) i cc 2s (ma) i cc 32s (ma) i ccl , i ccl s, i cct ( a) i cch ( a)
mb95110a series 62 ? mb95116a current temperature characteristics f ch = 21 [mhz], f cl = 32.768 [khz] v cc = 3.3 [v] 12 10 8 6 4 2 0 ? 50 0 +50 +100 +150 i cc 2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ? 50 0 +50 +100 +150 i cc 32 7 6 5 4 3 2 1 0 ? 50 0 +50 +100 +150 i cc 2s 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ? 50 0 +50 +100 +150 i cc 32s 40 35 30 25 20 15 10 5 0 ? 50 0 +50 +100 +150 i ccl 3 16 14 12 10 8 6 4 2 0 ? 50 0 +50 +100 +150 i ccl s3 6 5 4 3 2 1 0 ? 50 0 +50 +100 +150 i cct 3 10 8 6 4 2 0 ? 2 ? 50 0 +50 +100 +150 i cch 3 i cct 3 ( a) i cch 3 ( a) i cc 2 (ma) i cc 32 (ma) i cc 2s (ma) i cc 32s (ma) i ccl 3 ( a) i ccl s3 ( a) t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c]
mb95110a series 63 ? mb95f118as/aw current temperature characteristics f ch = 21 [mhz], f cl = 32.768 [khz] v cc = 3.3 [v] 12 10 8 6 4 2 0 ? 50 0 +50 +100 +150 i cc 2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ? 50 0 +50 +100 +150 i cc 32 7 6 5 4 3 2 1 0 ? 50 0 +50 +100 +150 i cc 2s 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ? 50 0 +50 +100 +150 i cc 32s 40 35 30 25 20 15 10 5 0 ? 50 0 +50 +100 +150 i ccl 3 16 14 12 10 8 6 4 2 0 ? 50 0 +50 +100 +150 i ccl s3 6 5 4 3 2 1 0 ? 50 0 +50 +100 +150 i cct 3 10 8 6 4 2 0 -2 ? 50 0 +50 +100 +150 i cch 3 i cct 3 ( a) i cch 3 ( a) i cc 2 (ma) i cc 32 (ma) i cc 2s (ma) i cc 32s (ma) i ccl 3 ( a) i ccl s3 ( a) t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c] t a [ c]
mb95110a series 64 ? mb95116a/mb95f118as/aw input characteristics 3 2 1 0 1234 v ih v il t a = + 25 [ c ] v in [v] v cc [v] 0.7 v cc 0.3 v cc 3 2 1 0 1234 t a = + 25 [ c ] v in [v] v cc [v] v ih v il 0.7 v cc 0.3 v cc 3 2 1 0 1234 v ih v il t a = + 25 [ c ] v in [v] v cc [v] 0.8 v cc 0.2 v cc 3 2 1 0 1234 v ih v il t a = + 25 [ c ] v in [v] v cc [v] 0.8 v cc 0.2 v cc 3 2 1 0 1234 t a = + 25 [ c ] v in [v] v cc [v] 0.7 v cc 0.3 v cc v ih /v il mb95f118as/aw hysteresis input characteristics of cmos input level mb95116a hysteresis input characteristics of cmos input level mb95f118as/aw hysteresis input characteristics mb95116a hysteresis input characteristics mb95f118as/aw cmos input characteristics
mb95110a series 65 ? mb95116a/mb95f118as/aw ?h? level output voltage characteristics v oh1 : output pin of other than p00 to p07 (min) v oh2 : p00 to p07 (min) 1.2 1 0.8 0.6 0.4 0.2 0 02 6 8 10 412 mb95f118as/aw v oh1 (t a = + 25 c) i oh [ma] v cc = 2.5 [v] v cc = 1.8 [v] v cc = 2.0 [v] v cc - v oh1 [v] v cc = 3.3 [v] v cc = 3.0 [v] 1.2 1 0.8 0.6 0.4 0.2 0 02 6 8 10 412 mb95116a v oh1 (t a = + 25 c) i oh [ma] v cc = 1.8 [v] v cc = 2.0 [v] v cc - v oh1 [v] v cc = 3.3 [v] v cc = 2.5 [v] v cc = 3.0 [v] 1.2 1 0.8 0.6 0.4 0.2 0 04 12 16 20 824 mb95f118as/aw v oh2 (t a = + 25 c) i oh [ma] v cc = 1.8 [v] v cc = 2.0 [v] v cc - v oh2 [v] v cc = 3.3 [v] v cc = 2.5 [v] v cc = 3.0 [v] 1.2 1 0.8 0.6 0.4 0.2 0 04 12 16 20 824 mb95116a v oh2 (t a = + 25 c) i oh [ma] v cc = 1. 8 [v] v cc = 2.0 [v] v cc - v oh2 [v] v cc = 3.3 [v] v cc = 2.5 [v] v cc = 3.0 [v]
mb95110a series 66 ? mb95116a/mb95f118as/aw ?l? level output voltage characteristics v oh1 : output pin of other than p00 to p07 (max) v oh2 : p00 to p07 (max) 600 500 400 300 200 100 0 02 6 8 10 412 mb95f118as/aw v ol1 (t a = + 25 c) i ol [ma] v cc = 1.8 [v] v cc = 2.0 [v] v ol1 [v] v cc = 2.5 [v] v cc = 3.0 [v] v cc = 3.3 [v] 600 500 400 300 200 100 0 02 6 8 10 412 mb95116a v ol1 (t a = + 25 c) i ol [ma] v cc = 1.8 [v] v cc = 2.0 [v] v ol1 [v] v cc = 3.3 [v] v cc = 2.5 [v] v cc = 3.0 [v] 600 500 400 300 200 100 0 04 12 16 20 824 mb95f118as/aw v ol2 (t a = + 25 c) i ol [ma] v ol2 [v] v cc = 3.3 [v] v cc = 2.5 [v] v cc = 3.0 [v] v cc = 1.8 [v] v cc = 2.0 [v] 600 500 400 300 200 100 0 04 12 16 20 824 mb95116a v ol2 (t a = + 25 c) i ol [ma] v cc = 1.8 [v] v ol2 [v] v cc = 3.3 [v] v cc = 2.0 [v] v cc = 2.5 [v] v cc = 3.0 [v]
mb95110a series 67 mask options * : low voltage detection reset is options of 5-v products. ordering information no part number mb95116a mb95f118as mb95f118aw mb95fv100b-101 specifying procedure specify when ordering mask setting disabled setting disabled setting disabled 1 clock mode select ? single-system clock mode ? dual-system clock mode selectable single-system clock mode dual-system clock mode changing by the switch on mcu board 2 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset no no no no 3 selection of oscillation stabilization wait time ? selectable the initial value of main clock oscillation stabilization wait time selectable 1 : ( 2 2 ? 2) /f ch 2 : ( 2 12 ? 2) /f ch 3 : ( 2 13 ? 2) /f ch 4 : ( 2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch part number package remarks MB95116APV2 mb95f118aspv2 mb95f118awpv2 48-pin plastic bcc (lcc-48p-m09) mb95116apmt mb95f118aspmt mb95f118awpmt 48-pin plastic lqfp (fpt-48p-m26) mb95116apmc mb95f118aspmc mb95f118awpmc 52-pin plastic lqfp (fpt-52p-m01) mb2146-301 (mb95fv100b-101pbt) mcu board ( ) 224-pin plastic pfbga (bga-224p-m08)
mb95110a series 68 package dimensions (continued) 4 8 -pin pl as tic bcc le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 7.00 mm 7.00 mm s e a ling method pl as tic mold mo u nting height 0. 8 0 mm m a x weight 0.06 g 4 8 -pin pl as tic bcc (lcc-4 8 p-m09) (lcc-4 8 p-m09) c 2004 fujit s u limited c4 8 062 s -c-1-1 1 1 3 3 7 25 5.00(.197) ref 6.25(.246) ref "c" "b" "a" 6.25(.246)ref 6.20(.244) typ 0.50 0.10 (.020 .004) 0.50(.020) typ 5.00(.197)ref 6.20(.244)typ 0.075 0.025 (.00 3 .001) 1 3 25 3 7 1 7.00 0.10(.276 .004) ( s t a nd off) 7.00 0.10 (.276 .004) 0.05(.002) det a il s of "c" p a rt 0.55 0.06 (.022 .002) 0.55 0.06 (.022 .002) index area det a il s of "a" p a rt (.026 .002) 0.65 0.06 (.012 .002) 0. 3 0 0.06 c0.2(.00 8 ) det a il s of "b" p a rt 0.14(.006) min (mo u nt height) (.0 3 0 .002) 0.75 0.05 typ 0.50(.020) 0.50 0.10 (.020 .004) 0.55 0.06 (.022 .002) 0.55 0.06 (.022 .002) ( 8 -.024 .002) 8 -0.60 0.06 6.15(.242)typ 6.15(.242) typ dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb95110a series 69 (continued) 4 8 -pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 7 7 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.17 g code (reference) p-lfqfp4 8 -7 7-0.50 4 8 -pin pl as tic lqfp (fpt-4 8 p-m26) (fpt-4 8 p-m26) c 200 3 fujit s u limited f4 8 040 s -c-2-2 24 1 3 3 625 4 8 3 7 index s q 9.00?.20(. 3 54?00 8 ) s q 0.145?.055 (.006?002) 0.0 8 (.00 3 ) "a" 0?~ 8 ? .059 ?004 +.00 8 ?.10 +0.20 1.50 0.60?.15 (.024?006) 0.10?.10 (.004?004) ( s t a nd off) 0.25(.010) det a il s of "a" p a rt 1 12 0.0 8 (.00 3 ) m (.00 8 ?002) 0.20?.05 0.50(.020) lead no. (mo u nting height) .276 ?004 +.016 ?.10 +0.40 7.00 * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb95110a series 70 (continued) 52-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x code (reference) p-lqfp52-10 10-0.65 52-pin pl as tic lqfp (fpt-52p-m01) (fpt-52p-m01) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 (.020 .00 8 ) 0.50 0.20 1.50 +0.20 0.10 +.00 8 .004 .059 0 ? ~ 8 ? "a" 0.10(.004) (.006 .002) 0.145 0.055 0.1 3 (.005) m 0.65(.026) 12.00 0.20(.472 .00 8 ) s q 10.00 0.10(. 3 94 .004) s q index 40 52 27 3 9 14 26 1 3 1 2005 fujit s u limited f52001 s -c-1-1 c (mo u nting height) .012 .0014 +.0027 0.0 3 5 +0.065 0. 3 0 * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb95110a series f0607 the information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/mic roelectronics/product/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

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